The present invention relates to programmable logic devices, particularly field programmable gate arrays (FPGAs). Lookup tables are highly configurable combinatorial logic devices. Their programming flexibility makes them desirable for use as basic building blocks in programmable logic devices (PLDs). Referring to FIG. 1, a generic implementation of a look-up table (LUT) in accordance with the prior art is shown. Generally, a lookup table includes an array of programmable architecture elements, such as SRAM cells 2, for storing data bits which are effectively used as output signals. Each one of the data bits corresponds to a particular set of input signals 1b.
A particular data bit 1b is coupled to the look-up table output terminal 1c by decoding multiplexer circuitry 1 that is controlled by the lookup table input signals. The inputs 1b and outputs 1c of the look-up table usually connect to the routing resources of the CPLD/FPGA. In many cases, the output 1c is also coupled to a sequential element (flip-flop, latch, etc.). The inputs 1b and outputs 1c can, of course, be connected to other devices.
A generic look-up table is used to implement any function that can be bounded within the inputs and outputs of the LUT. Larger functions are broken down into smaller functions tailored to fit into the LUTs. The device routing resources connect these LUTs. Typically, in a circuit netlist mapped into LUTs, multiple LUTs are used to implement identical or similar functionality. An example of this would be an adder implementation in which the number of LUTs programmed to perform addition is directly proportional to the number of bits being added. It follows that a plurality of LUTs would be programmed with the same set of configuration bits. As will be discussed further below, numerous such scenarios exist.